SH7764 Datasheet, PDF (53/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 24.10 Example of Register Settings for T-1004 Output............................................ 1273
Section 25 NAND Flash Memory Controller (FLCTL)
Table 25.1 Pin Configuration................................................................................................ 1281
Table 25.2 Register Configuration of FLCTL ...................................................................... 1282
Table 25.3 Register State of FLCTL in Each Processing Mode ........................................... 1283
Table 25.4 Status Read of NAND-Type Flash Memory....................................................... 1315
Table 25.5 FLCTL Interrupt Requests.................................................................................. 1316
Table 25.6 DMA Transfer Specifications ............................................................................. 1316
Section 26 Sampling Rate Converter (SRC)
Table 26.1 Register Configuration........................................................................................ 1319
Table 26.2 State of Registers in Each Operating Mode ........................................................ 1319
Table 26.3 Alignment of Data before Sampling Rate Conversion........................................ 1320
Table 26.4 Alignment of Data in SRCOD ............................................................................ 1321
Table 26.5 Relationship between Sampling Rate Setting and Number of Output Data........ 1328
Table 26.6 Interrupt Requests and Generation Conditions ................................................... 1335
Section 27 General Purpose I/O (GPIO)
Table 27.1 Multiplexed Pins Controlled by Port Control Registers...................................... 1338
Table 27.2 Multiplexed Pins Controlled by Pin Select Registers ......................................... 1343
Table 27.3 Register Configuration........................................................................................ 1346
Table 27.4 Register States in Each Operating Mode ............................................................ 1348
Section 28 Power-Down Mode
Table 28.1 States in Power-Down Modes............................................................................. 1412
Table 28.2 Pin Configuration................................................................................................ 1413
Table 28.3 Register Configuration........................................................................................ 1413
Table 28.4 Register States in Each Operating Mode ............................................................ 1413
Section 29 Watchdog Timer and Reset
Table 29.1 Pin Configuration................................................................................................ 1427
Table 29.2 Register Configuration........................................................................................ 1428
Table 29.3 Register States in Each Processing Mode ........................................................... 1428
Section 30 User Break Controller (UBC)
Table 30.1 Register Configuration........................................................................................ 1443
Table 30.2 Register Status in Each Processing State ............................................................ 1444
Table 30.3 Settings for Match Data Setting Register............................................................ 1456
Table 30.4 Relation between Operand Sizes and Address Bits to be Compared .................. 1464
Section 31 User Debugging Interface (H-UDI)
Table 31.1 Pin Configuration................................................................................................ 1479
Table 31.2 Commands Supported by Boundary-Scan TAP Controller ................................ 1481
Rev. 1.00 Nov. 22, 2007 Page liii of lvi