SH7764 Datasheet, PDF (1251/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
c = INT. INE
d = TRA. TRE
Bit 18—Matrix Operation Error Flag Enable (MTE): Enables or disables interrupts initiated
by the MTRER flag in SR.
Note:
The MTRER bit is not masked by the coordinate transformation enable bit (GTE) in the
coordinate transformation control register (GTRCR) or the rendering attribute MTRE bit.
Thus, when GTE = 0 or when GTE = 1 with MTRE = 0, the MTRER bit may be set to 1
even when coordinate transformation is not performed. Therefore, do not use the MTRER
bit unless both the GTE and MTRE bits are set to 1 throughout the period from rendering
start to TRAP command issuance.
Bit 18: MTE
0
1
Description
Interrupts initiated by the MTRER flag in SR are disabled. (Initial value)
Interrupts initiated by the MTRER flag in SR are enabled.
Bit 2—Command Error Flag Enable (CEE): Enables or disables interrupts initiated by the CER
flag in SR.
Bit 2: CEE
0
1
Description
Interrupts initiated by the CER flag in SR are disabled. (Initial value)
Interrupts initiated by the CER flag in SR are enabled.
Bit 1—Interrupt Flag Enable (INE): Enables or disables interrupts initiated by the INT flag in
SR.
Bit 1: INE
0
1
Description
Interrupts initiated by the INT flag in SR are disabled. (Initial value)
Interrupts initiated by the INT flag in SR are enabled.
Bit 0—Trap Flag Enable (TRE): Enables or disables interrupts initiated by the TRA flag in SR.
Bit 0: TRE
0
1
Description
Interrupts initiated by the TRA flag in SR are disabled. (Initial value)
Interrupts initiated by the TRA flag in SR are enabled.
Bits 31 to 19 and 17 to 3—Reserved: The write value should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1195 of 1692
REJ09B0360-0100