SH7764 Datasheet, PDF (415/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Section 12 Direct Memory Access Controller (DMAC)
This LSI includes the direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
12.1 Features
• Six channels (two channels can receive an external request: channels 0 and 1)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), 16 bytes, and 32
bytes
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode
• Transfer requests:
External request (channels 0 and 1), on-chip peripheral module request (channels 0 to 5), or
auto request can be selected.
The following modules can issue an on-chip peripheral module request.
 SCIF0, SCIF1, SCIF2, USB, FLCTL, and SRC
• Selectable bus modes:
Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
• Selectable channel priority levels:
The channel priority levels are selectable between fixed mode and round-robin mode.
• Interrupt request: An interrupt request can be generated to the CPU after half of the transfers
ended, all transfers ended, or an address error occurred.
• External request detection: There are following four types of DREQn input detection.
(n = 0, 1)
 Low level detection (Initial value)
 High level detection
 Rising edge detection
 Falling edge detection
Rev. 1.00 Nov. 22, 2007 Page 359 of 1692
REJ09B0360-0100