SH7764 Datasheet, PDF (316/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.3 Area Overview
11.3.1 Space Divisions
The architecture of this LSI provides a 32-bit virtual address space. The virtual address space is
divided into five areas according to the upper address value. The external memory space indicated
by the remaining 29 address bits is divided into four areas.
The virtual addresses can be allocated to any external address using the address translation
function of the MMU. For details, see section 7, Memory Management Unit (MMU). This section
describes the area division of the external address space.
With this LSI, SRAM or SDRAM can be connected to each of the four areas in the external
address space as shown in table 11.2.
H'0000 0000
P0 and
U0 areas
256
P0 and
U0 areas
Area 0 (CS0)
Area 1 (CS1)
Area 2 (CS2)
Area 3 (CS3)
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'8000 0000
P1 area
H'A000 0000
P2 area
H'C000 0000
P3 area
H'E000 0000 _{Store queue area}
H'E400 0000
H'FFFF FFFF
P4 area
P1 area
P2 area
P3 area
Store queue area
P4 area
H'1FFF FFFF
Notes:
1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and
memory is mapped onto a fixed 29-bit external address.
2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be
mapped onto any external space using the TLB.
For details, see section 7, Memory Management Unit (MMU).
Figure 11.2 Correspondence between Virtual Address Space and External Memory Space
Rev. 1.00 Nov. 22, 2007 Page 260 of 1692
REJ09B0360-0100