SH7764 Datasheet, PDF (59/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Items
FPU
Section 1 Overview
Specification
• On-chip floating-point coprocessor
• Supports single precision (32 bits) and double precision (64 bits)
• Supports IEEE754-compliant data types and exceptions
• Two rounding modes: Round to Nearest and Round to Zero
• Handling of denormalized numbers: Truncation to zero or interrupt
generation for compliance with IEEE754
• Floating-point registers: 32 bits x 16 words x 2 banks
(single-precision x 16 words or double-precision x 8 words) x 2 banks
• 32-bit CPU-FPU floating-point communication register (FPUL)
• Supports FMAC (multiply-and-accumulate) instruction
• Supports FDIV (divide) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution time:
 Latency (FADD/FSUB): 3 cycles (single-precision) or 5 cycles
(double-precision)
 Latency (FMAC/FMUL): 5 cycles (single-precision) or 7 cycles
(double-precision)
 Pitch (FADD/FSUB): 1 cycle (single-precision) or 1 cycle (double-
precision)
 Pitch (FMAC/FMUL): 1 cycle (single-precision) or 3 cycles (double-
precision)
Note: FMAC is supported for single-precision only.
• 3-D graphics instructions (single-precision only)
 4-dimensional vector conversion and matrix operations (FTRV): 4
cycles (pitch), 8 cycles (latency)
 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 5 cycles
(latency)
• 11-stage pipeline
Rev. 1.00 Nov. 22, 2007 Page 3 of 1692
REJ09B0360-0100