SH7764 Datasheet, PDF (312/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Figure 11.1 shows the block diagram of the MMU.
Super Hyway bus
LCDC bus
Pixel bus
SHIF
64 bits
Alignment
Linear to tiled memory
address translation
256 bits
LCDIF
64 bits
256 bits
Alignment
256 bits
Read data
buffer
Alignment
PXIF
32 bits
64 bits 128 bits
32 64 128
bits bits bits
Arbitration
Arbitration
Arbitration
Command and
write data buffer
Alignment
Linear to tiled memory
address translation
Read data
buffer
Alignment
64 bits
256 bits
64 bits
256 bits 256 bits 256 bits
Level 3 Level 2 Level 1
64 bits
ARBT
Inter-area request control
Arbitration
Bus release control
Inter-area response control
LBSC
SRAM bus controller
(areas 0 and 3)
Registers
SBSC
SDRAM bus controller
(areas 1 and 2)
Figure 11.1 Block Diagram of MCU
Rev. 1.00 Nov. 22, 2007 Page 256 of 1692
REJ09B0360-0100