SH7764 Datasheet, PDF (1049/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
S
S
SOD S
SOD S
SOD
(µ) frame
O
F
O
F
OUA O
FTT F
OUA O
FTT F
OUA
FTT
A
A
A
0
0
0
PID bit setting
Token
NAK
BUF
BUF
BUF
BUF
BUF
BUF
Token
Token
Token
Token
Token
Token
Token
reception reception reception reception reception reception reception
is not waited is not waited is waited is not waited is waited is not waited is waited
Interval counter started
Figure 21.15 Relationship between (µ) Frames and Expected Token Reception
when IITV ≠ 0
(ii) When the selected pipe is for isochronous IN transfers
The IFIS bit should be 1 for this use. When IFIS = 0, this module transmits a data packet in
response to the received IN token irrespective of the IITV bit setting.
When IFIS = 1, this module clears the FIFO buffer when this module fails to receive an IN token
within the interval set by the IITV bits in terms of (µ) frames in a state in which there is data to be
transmitted in the FIFO buffer.
This module also clears the FIFO buffer when this module fails to receive an IN token
successfully because of a bus error such as a CRC error contained in the token.
This module clears the FIFO buffer on receiving an SOF packet. Even if the SOF packet is
corrupted, the internal interpolation is used and allows the FIFO buffer to be cleared at the timing
to receive the SOF packet.
The interval counting starts at the different timing depending on the IITV bit setting (similar to the
timing during OUT transfers).
The interval is counted on any of the following conditions in function controller mode.
 When a hardware-reset is applied to this module (here, the IITV bits are also cleared to 0).
 When software sets the ACLRM bit to 1.
 When this module detects a USB reset.
Rev. 1.00 Nov. 22, 2007 Page 993 of 1692
REJ09B0360-0100