SH7764 Datasheet, PDF (717/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name
Value R/W Description
0
RXFIFOEMP0 1
R/W Receive FIFO Empty 0 (3)
(RXFIFOEMP3)
Indicates that the receive FIFO buffer for SSI_CH0
(CH3) is empty.
0: Indicates that the receive FIFO buffer for SSI_CH0
(CH3) is not empty.
1: Indicates that the receive FIFO buffer for SSI_CH0
(CH3) is empty.
Note: Descriptions within parenthesis "( )" indicate those for SSIDMINTSR1.
18.3.15 Interrupt Mask Registers 0 and 1 (SSIDMINTMR0 and SSIDMINTMR1)
SSIDMINTMR0 and SSIDMINTMR1 are 32-bit readable/writable registers that mask interrupts
sources of SSI_DMAC0/1 other than the port function. This register value is initialized when
either of the conditions is implemented such as hardware reset, software reset or software reset for
SSI_DMAC (DMRST bit in SSIDMACOR0 to SSIDMACOR3)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16











BLKEND BLKN DMEND TXFIFO RXFIFO
M2 ENDM2 M2 FULM2 EMPM2
Initial value: 0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0



BLKEND BLKN DM TXFIFO RXFIFO
M1 ENDM1 ENDM1 FULM1 EMPM1



BLKEMD BLKN DMEND TXFIFO RXFIFO
M0 ENDM0 M0 FULM0 EMPM0
Initial value: 0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
R/W: R
R
R R/W R/W R/W R/W R/W R
R
R R/W R/W R/W R/W R/W
Bit
31 to 29
Bit Name

28 to 24 
23 to 21 
Initial
Value
All 0
All 1
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
be the same as read value.
R Reserved
These bits are always read as 1. The write value should
be the same as read value.
R Reserved
These bits are always read as 0. The write value should
be the same as read value.
Rev. 1.00 Nov. 22, 2007 Page 661 of 1692
REJ09B0360-0100