SH7764 Datasheet, PDF (1269/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
Bit 0—Affine Transformation Enable (AFE): Does not perform W division and offset addition
at coordinate transformation. This bit is enabled when both the rendering attribute MTRE bit and
GTE bit are set to 1.
Bit 0: AFE
0
1
Description
The vertex coordinates X', Y' are obtained by dividing the matrix operation result
coordinates TX, TY by WC, and then adding the offset values.
X' = TX/WC + GTROFSX
Y' = TY/WC + GTROFSY
GTROFSX and GTROFSY are set in the coordinate transformation offset X
register (GTROFSX) and coordinate transformation offset Y register (GTROFSY),
respectively. (Initial value)
The vertex coordinates X', Y' are the matrix operation result coordinates
TX, TY.
X' = TX
Y' = TY
Bits 30 to 1—Reserved: The write value should always be 0. These bits are always read as 0.
(2) Matrix Parameter A Register (MTRAR)
Offset:
H'104
Initial Value: Undefined
The matrix parameter A register (MTRAR) is a 32-bit readable/writable register which specifies a
matrix parameter at coordinate change in the single-precision floating-point format defined by the
IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point
operations (16-bit integer portion and 16-bit fractional portion), MTRAR should be set within the
range of −2¹⁵ ≤ MTRAR < 2¹⁵.
MTRAR retains its value at a reset.
Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate
Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions.
Rev. 1.00 Nov. 22, 2007 Page 1213 of 1692
REJ09B0360-0100