SH7764 Datasheet, PDF (356/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Bit
3 to 0
Initial
Bit Name Value R/W
IW3 to IW0 1111 R/W
Description
These bits specify the number of wait cycles to be
inserted during an access to the CSn space.
When 0000 is set (wait cycles are not inserted),
external wait insertion using the RDY pin is disabled.
0000: No wait cycles inserted
0001: 1 wait cycle inserted
0010: 2 wait cycles inserted
0011: 3 wait cycles inserted
0100: 4 wait cycles inserted
0101: 5 wait cycles inserted
0110: 6 wait cycles inserted
0111: 7 wait cycles inserted
1000: 8 wait cycles inserted
1001: 9 wait cycles inserted
1010: 11 wait cycles inserted
1011: 13 wait cycles inserted
1100: 15 wait cycles inserted
1101: 17 wait cycles inserted
1110: 21 wait cycles inserted
1111: 25 wait cycles inserted
Rev. 1.00 Nov. 22, 2007 Page 300 of 1692
REJ09B0360-0100