SH7764 Datasheet, PDF (517/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
Interrupt Source
INTEVT
Code
Interrupt MASK/CLEAR
Priority Register
Interrupt
Source
Register
Detail
Source
Register
Priority
in the
Source
SCIF2
ERI2
RXI2
BRI2
TXI2
H'F00
H'F20
H'F40
H'F60
INT2PRI7
[28:24]
INT2MSKR1[25]
INT2MSKCR1[25]
INT2A01
[25]
INT2A11
[25]
INT2B6[0] High
INT2B6[1]
INT2B6[2]
INT2B6[3] ^Low
GPIO
CH0
CH1
H'F80
H'FA0
INT2PRI7
[20:16]
INT2MSKR[25]
INT2MSKCR[25]
INT2A0[25] INT2B7
INT2A1[25] ^[3:0]
INT2B7
[11:8]
High
CH2
H'FC0
INT2B7
[19:16]
CH3
H'FE0
INT2B7
[27:24]
Low
Note:
* ITI: Interval timer interrupt
TUNI0 to TUNI5: TMU channel 0 to 5 under flow interrupt
TICPI2: TMU channel 2 input capture interrupt
DMINT0 to DMINT5: DMAC channel 0 to 5 transfer end interrupt
DMAE: DMAC address error interrupt (channel 0 to 5)
ERI0, ERI1, ERI2: SCIF channel 0, 1,2 receive error interrupt
RXI0, RXI1, RXI2: SCIF channel 0, 1,2 receive data full interrupt
BRI0, BRI1, BRI2: SCIF channel 0, 1,2 break interrupt
TXI0, TXI1, TXI1: SCIF channel 0, 1,2 transmission data empty interrupt
Default
Priority
High
Low
Rev. 1.00 Nov. 22, 2007 Page 461 of 1692
REJ09B0360-0100