SH7764 Datasheet, PDF (1012/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
generated even if a new USB request is received. (This module retains the setup stage end, and
after the interrupt status has been cleared by software, a setup stage end interrupt is generated.)
Setup
token reception
CTSQ = 000
setup stage
Setup token reception
CTSQ = 110
control transfer
sequence error
5
Error
detection
Setup token reception
Error detection and IN token reception
are valid at all stages in the box.
ACK
trans-
mission
CTSQ = 001
1 control read
data stage
OUT token
2
CTSQ = 010
control read
status stage
ACK
trans-
mission
4
CTSQ = 000
idle stage
4
ACK
transmission
1
CTSQ = 011
control write
data stage
IN token
3
CTSQ = 100
control write
status stage
ACK
reception
ACK
transmission
Note:
CTRT interrupts
(1) Setup stage completed
(2) Control read transfer status stage transition
(3) Control write transfer status stage transition
(4) Control transfer completed
(5) Control transfer sequence error
CTSQ = 101
1
control write
no data
status stage
ACK
reception
Figure 21.7 Control Transfer Stage Transitions
(6) Frame Update Interrupt
Figure 21.8 shows an example of the SOFR interrupt output timing of this module. With the host
controller function selected, an interrupt is generated at the timing at which the frame number is
updated. With the function controller function selected, the SOFR interrupt is generated when the
frame number is updated.
When the function controller function is selected, this module updates the frame number and
generates an SOFR interrupt if it detects a new SOF packet during full-speed operation. During
high-speed operation, however, this module does not update the frame number, or generates no
SOFR interrupt until the module enters the µSOF locked state. Also, the SOF interpolation
function is not activated. The µSOF lock state is the state in which µSOF packets with different
frame numbers are received twice continuously without error occurrence.
The conditions under which the µSOF lock monitoring begins and stops are as follows.
Rev. 1.00 Nov. 22, 2007 Page 956 of 1692
REJ09B0360-0100