SH7764 Datasheet, PDF (1743/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Multiple virtual memory mode ............... 156
N
NMI (nonmaskable interrupt) ................. 126
NMI interrupt.......................................... 455
Notes on display-off mode
(LCDC stopped) ................................... 1049
O
On-chip module interrupts...................... 456
On-Chip peripheral module request
mode ....................................................... 386
Operand access cycle break .................. 1464
Operation in asynchronous mode ........... 530
Operation in clocked synchronous
mode ....................................................... 541
Output Addition Circuit........................ 1657
Overflow................................................. 144
P
P0, P3, and U0 areas ............................... 153
P1 area .................................................... 154
P2 area .................................................... 154
P4 area .................................................... 154
Page size bits .......................................... 171
Pair single-precision data transfer
instructions ............................................. 147
Physical address space............................ 155
Pin arrangement........................................ 14
Pipelining.................................................. 71
Power-Down mode ............................... 1411
Power-down state ..................................... 47
Power-on reset ........................................ 108
Power-on/Power-off Sequence ............. 1574
Power-supply control sequences........... 1044
PPN......................................................... 171
Pre-execution user break/post-execution
user break................................................ 124
Privileged mode ........................................ 32
Processing modes...................................... 32
Programming model.................................. 31
Protection key data.................................. 171
R
Receive data sampling timing and
receive margin (asynchronous mode) ..... 551
Receive descriptor................................... 791
Registers
APR..................................................... 728
BEMPENB.......................................... 849
BEMPSTS........................................... 868
BRDYENB ......................................... 845
BRDYSTS .......................................... 864
BUSWAIT .......................................... 815
CAMR0............................................. 1454
CAMR1............................................. 1454
CAR0 ................................................ 1453
CAR1 ................................................ 1453
CBCR................................................ 1460
CBR0 ................................................ 1445
CBR1 ................................................ 1445
CCMFR............................................. 1459
CCR .................................................... 212
CDCR.................................................. 718
CDMR1............................................. 1457
CDR1 ................................................ 1456
CEFCR................................................ 721
CETR1 .............................................. 1458
CFIFO ................................................. 827
CFIFOCTR ......................................... 837
CFIFOSEL .......................................... 830
CHCR.................................................. 370
CPUOPM .......................................... 1659
CRR0 ................................................ 1451
CRR1 ................................................ 1451
Rev. 1.00 Nov. 22, 2007 Page 1687 of 1692
REJ09B0360-0100