SH7764 Datasheet, PDF (504/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.18 On-Chip Module Interrupt Source Registers (INT2B0 and INT2B2 to INT2B7)
INT2B0 and INT2B2 to INT2B7 are 32-bit read-only registers that indicate detailed sources for
interrupt source modules indicated in the interrupt source register. INT2B0 and INT2B2 to
INT2B7 are not affected by the mask state of the interrupt mask register. When mask setting is
made for individual detailed sources, set the interrupt mask register or interrupt enable register in
the corresponding modules.
The initial value of these registers is undefined (reserve bit is always read as 0).
Bit: _{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Initial value: _{               }
R/W: _{R R R R R R R R R R R R R R R R}
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: _{               }
R/W: R R R R R R R R R R R R R R R R
INT2B0: Indicates detailed interrupt sources for the TMU.
Module
TMU
Bit
31 to 7
6
5
4
3
2
1
0
Source Function
Description
—
TUNI5
TUNI4
TUNI3
TICPI2
These bits are always read as 0. The Indicates TMU interrupt
write value should always be 0.
sources. This register
TMU channel 5 underflow interrupt
indicates the TMU
interrupt sources even if
TMU channel 4 underflow interrupt mask setting is made in
TMU channel 3 underflow interrupt
the interrupt mask
register for them.
TMU channel 2 input capture interrupt
TUNI2 TMU channel 2 underflow interrupt
TUNI1 TMU channel 1 underflow interrupt
TUNI0 TMU channel 0 underflow interrupt
Rev. 1.00 Nov. 22, 2007 Page 448 of 1692
REJ09B0360-0100