SH7764 Datasheet, PDF (475/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.1 Interrupt Control Register 0 (ICR0)
ICR0 sets the input signal detection mode of NMI pin, and indicates the input level to the NMI
pin.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIL MAI     NMIB NMIE        
Initial value: — 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
R/W: R R/W R R R R R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value
R/W
31
NMIL
Undefined R
30
MAI
0
R/W
29 to 26 
All 0
R
Description
NMI Input Level
Sets the signal level input to the NMI pin. Reading this
bit allows the user to know the NMI pin level, and
writing is invalid.
0: Low level is input to the NMI pin
1: High level is input to the NMI pin
MAI Interrupt Mask
Specifies whether all interrupts are masked during the
low level period of the NMI pin level regardless of the
BL bit in SR of the CPU.
0: Interrupts are enabled even if the NMI pin goes low
1: Interrupts are disabled if the NMI pin goes low
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 419 of 1692
REJ09B0360-0100