SH7764 Datasheet, PDF (1353/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
23, 22 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
21, 20 FIFOTRG 00
[1:0]
R/W FIFO Trigger Setting
Change the condition for the FIFO transfer request.
In flash-memory read:
00: Issue an interrupt or a DMA transfer request to the
CPU when FLDTFIFO stores 4 bytes of data.
01: Issue an interrupt or a DMA transfer request to the
CPU when FLDTFIFO stores 16 bytes of data.
10: Issue an interrupt or a DMA transfer request to the
CPU when FLDTFIFO stores 128 bytes of data.
11: Issue an interrupt to the CPU when FLDTFIFO
stores 128 bytes of data, or issue a DMA transfer
request to the CPU when FLDTFIFO stores 16
bytes of data.
In flash-memory programming:
00: Issue an interrupt to the CPU when FLDTFIFO has
empty area of 4 bytes or more (do not set DMA
transfer).
01: Issue an interrupt or a DMA transfer request to the
CPU when FLDTFIFO has empty area of 16 bytes
or more.
10: Issue an interrupt to the CPU when FLDTFIFO has
empty area of 128 bytes or more (do not set DMA
transfer).
11: Issue an interrupt to the CPU when FLDTFIFO has
empty area of 128 bytes or more, or issue a DMA
transfer request to the CPU when FLDTFIFO has
empty area of 16 bytes or more.
19
AC1CLR 0
R/W FLECFIFO Clear
Clears FLECFIFO.
0: Retains the FLECFIFO value. In flash-memory
access, this bit should be cleared to 0.
1: Clears FLECFIFO. After FLECFIFO has been
cleared, this bit should be cleared to 0.
Rev. 1.00 Nov. 22, 2007 Page 1297 of 1692
REJ09B0360-0100