SH7764 Datasheet, PDF (1513/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 User Break Controller (UBC)
30.2.6 Match Data Mask Setting Register 1 (CDMR1)
CDMR1 is a readable/writable 32-bit register which specifies the bits to be masked among the
data value bits specified using the match data setting register. (Set the bits to be masked to 1.)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDM
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CDM
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W
31 to 0 CDM
Undefined R/W
Description
Compare Data Value Mask
Specifies the bits to be masked among the data value
bits specified using the CDR1 register. (Set the bits to
be masked to 1.)
0: Data value bits CD[n] are included in the break
condition.
1: Data value bits CD[n] are masked and not included
in the break condition.
[n] = any values from 31 to 0
Rev. 1.00 Nov. 22, 2007 Page 1457 of 1692
REJ09B0360-0100