SH7764 Datasheet, PDF (372/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.5.2 Data Alignment in Various Modules
The endian mode in the MCU matches that in the CPU, and either big endian or little endian can
be used. Data should be aligned in each of the modules connected to the SuperHyway bus, the
modules connected to the pixel bus, and the LCDC connected to the LCD bus according to their
own bus width.
11.6 SRAM Interface
11.6.1 Basic Timing
The strobe signals for the SRAM interface of this LSI are output primarily based on the SRAM
connection. Figure 11.4 shows the basic timing of the SRAM interface. A no-wait normal access
is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus
cycle. The CS0 and CS3 signal is asserted at the rising edge of the clock in the T1 state, and
negated at the next rising edge of the clock in the T2 state. Therefore, there is no negation period
in the case of access at minimum pitch.
During reading, specification of an access size is not needed. The output of an access address on
the address pins (A25 to A0) is correct, however, since the access size is not specified, 32-bit data
is always output when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in
use. During writing, only the WE signal corresponding to the byte to be written is asserted. For
details, see section 11.5.1, Endian/Access Size and Data Alignment.
In 32-byte transfer, a total of 32 bytes are transferred continuously according to the bus width set.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wrap around method according to the set bus width. The bus is not
released during this transfer.
Rev. 1.00 Nov. 22, 2007 Page 316 of 1692
REJ09B0360-0100