SH7764 Datasheet, PDF (975/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Bit
Bit Name
13
CSCLR
12
CSSTS
11, 10 
Section 21 USB 2.0 Host/Function Module (USB)
Initial
Value
0
0
All 0
R/W
R/W*¹
R
R
Description
C-SPLIT Status Clear Bit
Setting this bit to 1 allows this module to clear the
CSSTS bit of the pertinent pipe to 0.
0: Writing invalid
1: Clears the CSSTS bit to 0.
For the transfer using the split transaction, to restart
the next transfer with the S-SPLIT forcibly, set this bit
to 1 through software. However, for the normal split
transaction, this module automatically clears the
CSSTS bit to 0 upon completion of the C-SPLIT;
therefore, clearing the CSSTS bit through software is
not necessary.
Controlling the CSSTS bit through this bit must be
done while UACT is 0 thus communication is halted
or while no transfer is being performed with bus
disconnection detected.
Setting this bit to 1 while CSSTS is 0 has no effect.
When the function controller function is selected, be
sure to write 0 to this bit.
CSSTS Status Bit
Indicates the C-SPLIT status of the split transaction
when the host controller function is selected.
0: START-SPLIT (S-SPLIT) transaction being
processed or the transfer not using the split
transaction in progress
1: C-SPLIT transaction being processed
This module sets this bit to 1 upon start of the C-
SPLIT and clears this bit to 0 upon detection of C-
SPLIT completion.
Indicates the valid value only when the host
controller function is selected.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 919 of 1692
REJ09B0360-0100