SH7764 Datasheet, PDF (355/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Bit
6 to 4
Initial
Bit Name Value R/W
BSH2 to 000 R/W
BSH0
Section 11 Memory Controller Unit (MCU)
Description
These bits specify the number of cycles to be inserted
to elongate the BS assertion time during an access to
the CSn space.
Cycle insertion is enabled when a value other than 000
is set in the RDS and WTS bits in CSnWCR in reading
and writing, respectively. The total number of access
cycles is not changed by the setting of these bits.
000: 1 cycle inserted for the BS assertion
001: 2 cycles inserted for the BS assertion
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Rev. 1.00 Nov. 22, 2007 Page 299 of 1692
REJ09B0360-0100