SH7764 Datasheet, PDF (29/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

28.5 Refresh Standby Mode..................................................................................................... 1421
28.5.1 Transition to Refresh Standby Mode .................................................................. 1421
28.5.2 Canceling Refresh Standby Mode....................................................................... 1421
28.6 Module Standby Mode..................................................................................................... 1422
28.6.1 Transition to Module Standby Mode .................................................................. 1422
28.6.2 Canceling Module Standby Mode....................................................................... 1422
28.7 STATUS Pin Signal Change Timing ............................................................................... 1423
28.7.1 Timing at Reset................................................................................................... 1423
28.7.2 Timing at Sleep Mode Cancellation.................................................................... 1423
Section 29 Watchdog Timer and Reset............................................................1425
29.1 Features............................................................................................................................ 1425
29.2 Input/Output Pins ............................................................................................................. 1427
29.3 Register Descriptions ....................................................................................................... 1428
29.3.1 Watchdog Timer Stop Time Register (WDTST) ................................................ 1429
29.3.2 Watchdog Timer Control/Status Register (WDTCSR)....................................... 1430
29.3.3 Watchdog timer Base Stop Time Register (WDTBST) ...................................... 1431
29.3.4 Watchdog Timer Counter (WDTCNT)............................................................... 1432
29.3.5 Watchdog Timer Base Counter (WDTBCNT) ................................................... 1432
29.4 Operation ......................................................................................................................... 1433
29.4.1 Reset request....................................................................................................... 1433
29.4.2 Using watchdog timer mode ............................................................................... 1434
29.4.3 Using Interval timer mode .................................................................................. 1434
29.4.4 Time for WDT Overflow .................................................................................... 1434
29.4.5 Clearing WDT Counter....................................................................................... 1435
29.5 Status Pin Change Timing during Reset .......................................................................... 1436
29.5.1 Power-On Reset by PRESET.............................................................................. 1436
29.5.2 Power-On Reset by Watchdog Timer Overflow................................................. 1439
Section 30 User Break Controller (UBC) ........................................................1441
30.1 Features............................................................................................................................ 1441
30.2 Register Descriptions ....................................................................................................... 1443
30.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ......................... 1445
30.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ......................... 1451
30.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)............................ 1453
30.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)........... 1454
30.2.5 Match Data Setting Register 1 (CDR1) .............................................................. 1456
30.2.6 Match Data Mask Setting Register 1 (CDMR1) ................................................. 1457
30.2.7 Execution Count Break Register 1 (CETR1) ...................................................... 1458
30.2.8 Channel Match Flag Register (CCMFR) ............................................................ 1459
Rev. 1.00 Nov. 22, 2007 Page xxix of lvi