SH7764 Datasheet, PDF (323/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit
Bit Name Value R/W
7, 6

All 0 R
5
BAD_OPC 0
R/W
4 to 2 
All 0 R
1
ERR_SNT 0
R/W
0

0
R
Section 11 Memory Controller Unit (MCU)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
This bit is set to 1 when a request that is not supported
by the MCU is received via the SuperHyway bus. This
bit is cleared by writing 0 to it.
Reserved
These bits are always read as 0. The write value
should always be 0.
This bit is set to 1 when the MCU returns an error
response via the SuperHyway bus. This bit is cleared
by writing 0 to it.
Reserved
This bit is always read as 0. The write value should
always be 0.
11.4.2 Memory Interface Mode Register (MIM)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
BOMODE[1:0]
 PCKE 







 SELFS RMODE 
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R/W R R R R R R R R R R R/W R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DRI[11:0]
Initial value: 0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






DRE ENDIAN
BW[1:0]
     DCE
Initial value: 0
0
0
0
0
0
0
*
0
1
0
0
0
0
0
0
R/W: R R R R R R R/W R R/W R/W R R R R R R/W
Rev. 1.00 Nov. 22, 2007 Page 267 of 1692
REJ09B0360-0100