SH7764 Datasheet, PDF (303/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 10 Clock Pulse Generator (CPG)
The functions of the blocks in the CPG are as follows.
(1) PLL Circuit 1
PLL circuit 1 multiples the frequency of the crystal oscillator or the clock input from the EXTAL
pin by the ratio of ×10 or ×12. The multiplication ratio is selected by the combination of mode
control pins MODE0, MODE1, and MODE2.
(2) PLL Circuit 2
PLL circuit 2 aligns the phases of the bus clock (Bck) and the clock signal output from the
CLKOUT pin that is used by the external peripheral interface.
(3) Crystal Oscillator
The crystal oscillator is a clock pulse generator used when a crystal resonator is connected to the
XTAL or EXTAL pin. The crystal oscillator can be enabled by the MODE8 pin setting.
(4) Divider 1
Divider 1 generates the CPU clock (Ick), SHwy clock (SHck), peripheral module clocks (Pck),
and bus clock (Bck).
(5) Frequency Control Register (FRQCR)
The frequency control register is a read-only register that shows the frequency division ratios for
the Ick, SHck, Pck, and Bck.
(6) PLL Control Register (PLLCR)
The PLL control register has control bits assigned for enabling or disabling the CLKOUT pin
output.
(7) Module Stop Registers (MSTPCR)
The module stop register has control bits for running/stopping the individual peripheral modules.
For the details of MSTPCR, see section 28, Power-Down Mode.
(8) Standby Control Register (STBCR)
The standby control register has bits for controlling the stand by modes. For the details of STBCR,
see section 28, Power-Down Mode.
Rev. 1.00 Nov. 22, 2007 Page 247 of 1692
REJ09B0360-0100