SH7764 Datasheet, PDF (639/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
(5) Wait for End of Transmission
1. Wait for the master event, MST in the master status register.
2. Reset the MST bit after confirming MNR (Master NACK Received).
16.5.2 Master Receiver
To set up the master interface to receive a data packet on the I²C bus, follow the following
procedure:
(1) Load Clock Control Register
1. SCL clock generation divider (SCGD) = H'03
(SCL frequency of 400 kHz).
2. Clock division ratio (CDF) = H'2
(The peripheral clock is 50 MHz and the IIC's internal clock IICck is 16.7 MHz.)
(2) Load Master Control Register and Address
1. Set master address register to address of slave being accessed and STM1 bit (read mode: 1).
2. Set master control register to H'89
(MDBS = 1, MIE = 1, ESG = 1).
(3) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDR bits in the master status register).
2. Set the master control register to H'88
(To suspend the data transmission, the master device will hold the SCL low until the MDR bit
is cleared).
If only one byte of data is received, set the master control register to H'8A, meaning that the
stop generation is enabled. This generates a stop on the bus as soon as one byte has been
received.
3. Reset the MAT bit.
(4) Monitor Reception of Data
1. Wait for master event, bit MDR in the master status register.
2. Read data from the received data register.
If the next byte of data is the second to last byte to be transmitted by the slave device, the
following applies to the receive interrupt (that is, MDR interrupt) in the second to last byte.
Rev. 1.00 Nov. 22, 2007 Page 583 of 1692
REJ09B0360-0100