SH7764 Datasheet, PDF (778/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.14 Frame Receive Error Counter Register (FRECR)
FRECR is a 32-bit counter that indicates the number of frames for which a receive error was
generated by the RX-ER pin input from the PHY-LSI. FRECR is incremented each time the RX-
ER pin becomes active. When the value in this register reaches H'FFFFFFFF, count-up is halted.
The counter value is cleared to 0 by a write to this register with any value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FREC[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FREC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 FREC[31:0] All 0 R/W Frame Receive Error Count
These bits indicate the number of errors during frame
reception.
Rev. 1.00 Nov. 22, 2007 Page 722 of 1692
REJ09B0360-0100