SH7764 Datasheet, PDF (1382/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
Initial
Bit
Bit Name Value R/W Description
10
EEN
0
R/W Output Data FIFO Overwrite Interrupt Enable
Enables/disables the output data FIFO overwrite
interrupt request to be issued when the data in the
output FIFO has been overwritten before being read
thus setting the OVF bit in SRC status register
(SRCSTAT) to 1.
0: Output data FIFO overwrite interrupt is disabled.
1: Output data FIFO overwrite interrupt is enabled.
9
FL
0
R/W Internal Work Memory Flush
Writing 1 to this bit starts converting the sampling rate
of all the data in the input FIFO, input buffer memory,
and intermediate memory (i.e., flush processing). This
bit is always read as 0. When SRCEN = 0, writing 1 to
this bit does not trigger flush processing.
If this bit is set to 1 while the number of data units in
the input buffer memory is less than 64, the flash
processing is not performed because valid output
data cannot be obtained.
8
CL
0
R/W Internal Work Memory Clear
Writing 1 to this bit clears the input FIFO, output
FIFO, input buffer memory, intermediate memory, and
accumulator. This bit is always read as 0.
Before operating the SRC, the SRC should be
internally cleared by writing 1 to this bit. To perform
the clearing processing correctly, wait 32 cycles of
peripheral bus clock after wring 1 to this bit and then
perform the next processing. In addition, when this bit
is set to 1, IFS[3:0] and OFS should also be set.
Rev. 1.00 Nov. 22, 2007 Page 1326 of 1692
REJ09B0360-0100