SH7764 Datasheet, PDF (1250/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
Bits 27 to 19 and 17 to 3—Reserved: These bits are always read as 0.
(3) Status Register Clear Register (SRCR)
Offset:
H'008
Initial Value: H'00000000
The status register clear register (SRCR) is a 32-bit write-only register that clears the
corresponding flags in the status register (SR). When SR clearing is completed, all of the values in
SRCR are cleared to 0 internally (the bits are read as 0).
Bit
Bit Name
Abbreviation
18
Matrix operation error MTCL
flag clear
2
Command error flag CECL
clear
1
Interrupt flag clear INCL
0
Trap flag clear
TRCL
31 to 19 Reserved
—
and 17 to
3
Description
Writing 1 to the MTCL bit clears the MTRER
flag in SR to 0.
Writing 1 to the CECL bit clears the CER flag
in SR to 0.
Writing 1 to the INCL bit clears the INT flag in
SR to 0.
Writing 1 to the TRCL bit clears the TRA flag in
SR to 0.
The write value should always be 0.
(4) Interrupt Enable Register (IER)
Offset:
H'00C
Initial Value: H'00000000
The interrupt enable register (IER) is a 32-bit readable/writable register that enables or disables
interrupts by the corresponding flags in the status register (SR). When a bit in SR is set to 1 and
the bit at the corresponding bit position in IER is also 1, an interrupt request is sent to the CPU.
The interrupt generation condition is as follows.
Interrupt generation condition = a + b + c + d
a = MTRER. MTE
b = CER. CEE
Rev. 1.00 Nov. 22, 2007 Page 1194 of 1692
REJ09B0360-0100