SH7764 Datasheet, PDF (645/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3 Register Description
The following ATAPI register set is allocated to the SH register map space.
Table 17.2 ATA Task File Register Map
(These resisters are allocated to the ATAPI or ATA device, and are not allocated to this module.)
Pin Address
(IDECS[1:0],
IDEA[2:0])
Address
Read Register
Write Register
H: High Level
L: Low Level
@3.3V I/O
Access Size*¹
(Available Bit Register
Size)
Location
H'FFF0 0000 Data
Data
H'FFF0 0004 Error
Function
H'FFF0 0008 Sector count Sector count
H'FFF0 000C Sector number Sector number
H'FFF0 0010 Cylinder low
Cylinder low
H'FFF0 0014 Cylinder high Cylinder high
H'FFF0 0018 Device/head Device/head
H'FFF0 001C Status
Command
H'FFF0 0038 Alternate status Device control
HL-LLL/HH-XXX
(X: Don't care)
HL-LLH
HL-LHL
HL-LHH
HL-HLL
HL-HLH
HL-HHL
HL-HHH
LH-HHL
32 (16)*²
32 (8)*³
32 (8)* ³
32 (8)* ³
32 (8)* ³
32 (8)* ³
32 (8)* ³
32 (8)* ³
32 (8)* ³
Drive
Drive
Drive
Drive
Drive
Drive
Drive
Drive
Drive
Notes: 1. These registers must be accessed in longwords (32 bits) by the CPU. Byte or word
accesses are prohibited.
2. Bits 15 to 0 of the data bus are used.
3. Bits 7 to 0 of the data bus are used.
Rev. 1.00 Nov. 22, 2007 Page 589 of 1692
REJ09B0360-0100