SH7764 Datasheet, PDF (283/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 Caches
privileged mode, and an address error exception occurs in user mode. TLB-related exceptions
do not occur.
Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H’F4, and their reserved areas (H’F0 to H’F3, H’F5
to H’FF).
8.5.2 Prefetch Operation
The SH-4A supports a prefetch instruction to reduce the cache fill penalty incurred as the result of
a cache miss. If it is known that a cache miss will result from a read or write operation, it is
possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a
cache miss due to the read or write operation, and so improve software performance. If a prefetch
instruction is executed for data already held in the cache, or if the prefetch address results in a
UTLB miss or a protection violation, the result is no operation, and an exception is not generated.
Details of the prefetch instruction are given in section 11, Instruction Descriptions of the SH-4A
Extended Functions Software Manual.
• Prefetch instruction (OC)
• Prefetch instruction (IC)
: PREF @Rn
: PREFI @Rn
Rev. 1.00 Nov. 22, 2007 Page 227 of 1692
REJ09B0360-0100