SH7764 Datasheet, PDF (500/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.16 Interrupt Mask Clear Register (INT2MSKCR)
INT2MSKCR is a 32-bit write-only register that clears any masking set in the interrupt mask
register. Setting bits in this register to 1 clears the masking of the corresponding interrupt sources.
Reading bits in this register is always 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
GPIO —
SRC FLCTL — ATAPI SSI_B —
SSI_A SSI_A
CH2 CH1
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSI_A SSI_A
CH0 DMA0
G2D
—
—
—
— DMAC H-UDI — WDT SCIF1 SCIF0 — TMU1 TMU0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Initial
Bit
Bit Name Value
31 to 26 —
All 0
25
GPIO
0
24
—
0
23
SRC
0
22
FLCTL 0
21
—
0
20
ATAPI 0
19
SSI_B 0
18
—
0
R/W Function
Description
W
Reserved
Clears interrupt
The write value should always be ^{masking for each}
0
peripheral module.
W
Clears GPIO interrupt masking ^{[When writing]}
W
Reserved
0: Invalid
The write value should always be
1: Interrupt mask is
cleared
0
W
Clears SRCOVF interrupt
[When reading]
masking
Always 0
W
Clears FLCTL interrupt masking
W
Reserved
The write value should always be
0
W
Clears ATAPI interrupt masking
W
Clears SSI_B interrupt masking
W
Reserved
The write value should always be
0
Rev. 1.00 Nov. 22, 2007 Page 444 of 1692
REJ09B0360-0100