SH7764 Datasheet, PDF (910/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
11
CTRT
0
R/W*⁷ Control Transfer Stage Transition Interrupt Status*⁴*⁶
0: Control transfer stage transition interrupts not
generated
1: Control transfer stage transition interrupts
generated
When the function controller function is selected, this
module updates the CTSQ value and sets this bit to
1 on detecting a change in the control transfer stage.
When this interrupt is generated, clear the status
before this module detects the next control transfer
stage transition.
When the host controller function is selected, the
read value is invalid.
10
BEMP
0
R
Buffer Empty Interrupt Status
0: BEMP interrupts not generated
1: BEMP interrupts generated
This module sets this bit to 1 when at least one
PIPEBEMP bit in BEMPSTS is set to 1 among the
PIPEBEMP bits corresponding to the PIPEBEMPE
bits in BEMPENB to which 1 has been set (when this
module detects the BEMP interrupt status in at least
one pipe among the pipes for which software
enables the BEMP interrupt output).
For the conditions for PIPEBEMP status assertion,
refer to (3) BEMP Interrupts under section 21.4.2,
Interrupt Functions.
This module clears this bit to 0 when software writes
0 to all the PIPEBEMP bits corresponding to the
PIPEBEMPE bits to which 1 has been set.
This bit cannot be cleared to 0 even if software writes
0 to this bit.
Rev. 1.00 Nov. 22, 2007 Page 854 of 1692
REJ09B0360-0100