SH7764 Datasheet, PDF (479/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.4 Interrupt Source Register (INTREQ)
INTREQ is a 32-bit readable and writable with conditions register that indicates which IRQ [n] (n
= 0, 1) interrupt is requested to the INTC.
Even if interrupts are masked by INTPRI and INTMSK, the INTREQ bits are not affected.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IR0 IR1 —
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Initial
Bit Name Value
31
IR0 0
30
IR1 0
29 to 0 
All 0
R/W
R/(W)
R/W
R
Description
At Edge Detection
(ICR1.IRQnS = 00 or 01,
n = 0, 1)
At Level Detection
(ICR1.IRQnS = 10 or 11,
n = 0, 1)
[When reading]
[When reading]
0: A corresponding IRQ
0: A corresponding IRQ
interrupt request is not
interrupt pin is not asserted
detected
1: A corresponding IRQ
1: A corresponding IRQ
interrupt pin has asserted,
interrupt request is detected but the CPU does not accept
[When writing]*
it yet
0: Each bit is cleared by writing ^{Writing is ignored.}
0 after reading 1
1: Holds detected interrupt
request
Note: * Write 1 to the
corresponding bit read
as 0.
Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 1.00 Nov. 22, 2007 Page 423 of 1692
REJ09B0360-0100