SH7764 Datasheet, PDF (571/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.5 lists the sample SCBRR settings in asynchronous mode in which a base clock
frequency is 16 times the bit rate (the ABCS bit in SCEMR is 0) and the baud rate generator
operates in normal mode (the BGDM bit in SCEMR is 0), and table 15.6 lists the sample SCBRR
settings in clock synchronous mode.
Table 15.5 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0)
Pch (MHz)
Bit
45
Rate
(bit/s) _n
N
110 3
199
150 3
145
300 3
72
600 2
145
1200 2
72
2400 1
145
4800 1
72
9600 0
145
19200 0
72
31250 0
44
38400 0
36
50
Error
(%)
n
-0.12 3
0.33 3
0.33 3
0.33 2
0.33 2
0.33 1
0.33 1
0.33 0
0.33 0
0.00 0
-1.02 0
54
Error
N
(%)
n
221
-0.02 3
162
-0.15 3
80
0.47 3
162
-0.15 2
80
0.47 2
162
-0.15 1
80
0.47 1
162
-0.15 0
80
0.47 0
49
0.00 0
40
-0.76 0
Error
N
(%)
239
-0.12
175
-0.12
87
-0.12
175
-0.12
87
-0.12
175
-0.12
87
-0.12
175
-0.12
87
-0.12
53
0.00
43
-0.12
Rev. 1.00 Nov. 22, 2007 Page 515 of 1692
REJ09B0360-0100