SH7764 Datasheet, PDF (1390/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
(1) When Interrupts are Issued to CPU
1. Set the OEN bit in SRCODCTRL to 1.
2. Set the interrupt controller.
3. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued. In the
interrupt processing routine, read the OINT bit and confirm that it is 1, read data from
SRCOD, and write 0 to the OINT bit. Then return from the interrupt processing routine.
4. After flush processing starts, repeat step 3 until the FLF bit in SRCSTAT is read as 0.
(2) When Interrupts are Used to Activate DMAC
1. Assign ODFI of the SRC to one channel of the DMAC.
2. Set the OEN bit in SRCODCTRL to 1.
3. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued thus activating
the DMAC. When the DMAC has read data from SRCOD thus resulting in the number of data
units in the output data FIFO being less than the triggering number specified by the OFTRG1
and OFTRG0 bits in SRCODCTRL, the OINT bit is cleared to 0.
4. After flush processing starts, repeat step 3 until the FLF bit in SRCSTAT is read as 0.
Rev. 1.00 Nov. 22, 2007 Page 1334 of 1692
REJ09B0360-0100