SH7764 Datasheet, PDF (466/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
NMI
IRQ1, IRQ0
2
Input
control
NMI
IRQ
Interrupt
Priority
determination
Comparator
USERIMASK.UIMASK
GPIO ports
PINT15 to
PINT0
GPIO interrupt
16
WDT
H-UDI
DMAC
Peripheral
module
Interrupt request
Interrupt request
Interrupt request
Interrupt request
INTPRI
ICR0, ICR1
On-chip Module
Interrupt
Priority
determination
Bus
interface
On-chip Module
INTC
INT2PRI0 to
INT2PRI12
INT2GPIC
Bus Interface
[Legend]
WDT:
Watch Dog Timer
H-UDI:
User Debugging Interface
DMAC:
Direct Memory Access Controller
INTPRI:
Interrupt Priority Level Setting Register
ICR0, ICR1:
Interrupt Control Register 0,1
INT2PRI0 to 12:
Interrupt Priority Regiter
INT2GPIC:
GPIO Interrupt set register
SR.IMASK:
Status Register. IMASK bit
USERIMASK.UIMASK: User interrupt mask level register UIMASK bit
Note: The following modules csn issue on-chip peripheral module interrupts
TMU, SCIF, VDC2, IIC, EtherC, G2D, SSI, ATAPI, USB, FLCTL, SRC, LCDC
Figure 13.1 Block Diagram of INTC
CPU
exception
handling
SR.IMASK
Rev. 1.00 Nov. 22, 2007 Page 410 of 1692
REJ09B0360-0100