SH7764 Datasheet, PDF (657/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Ultra DMA timing register value table
Pixel bus clock Mode 0
100MHz
H'0191
Mode 1
H'010E
Mode 2
H'00CB
Section 17 ATAPI
Mode 3
H'00AB
Mode 4
H'006B
17.3.7 Descriptor Table Base Address Register (ATAPI_DTB_ADR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
DTBAA[2:0]
DTBA[25:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTBA[15:2]
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R
Initial
Bit
Bit Name Value R/W
Description
31 to 29 —
All 0
R
Reserved
28 to 26 DTBAA 0
[2:0]
R/W
DTBA shows the descriptor table base SDRAM area
001: SDRAM area 1
010: SDRAM area 2
Other than above: Setting prohibited.
25 to 2 DTBA
0
[25:2]
R/W
DTBA shows the descriptor table base address.
Bits 25 to 0 are used to set the descriptor table base
address on a byte basis.
Bits 3 and 2 must be set 0, and bits 1 and 0 are
ignored because it is necessary to secure the
boundary of 64-bit addresses in the descriptor table.
1, 0
—
All 0
R
Reserved
Notes: 1. This register is valid only when bit 5 (BUSSEL) in the ATAPI Control Register is set to
1.
2. This address will not change and will retain its setting even after the DMA becomes
active.
3. In the 32-bit address mode, bits 28 to 0 should contain the lower 29 bits of the specified
32-bit address.
Rev. 1.00 Nov. 22, 2007 Page 601 of 1692
REJ09B0360-0100