SH7764 Datasheet, PDF (1580/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 32 List of Registers
Module
EtherC
Register Name
P4 Area
Abbreviation R/W Address*
Area 7
Address*
Access
Size Remarks
Lost carrier counter
register
LCCR
R/W H'FEF0 01D8* H'1EF0 01D8* 32
Carrier not detect
counter register
CNDCR
R/W H'FEF0 01DC* H'1EF0 01DC* 32
CRC error frame receive CEFCR
counter register
R/W H'FEF0 01E4* H'1EF0 01E4* 32
Frame receive error
counter register
FRECR
R/W H'FEF0 01E8* H'1EF0 01E8* 32
Too-short frame receive TSFRCR
counter register
R/W H'FEF0 01EC* H'1EF0 01EC* 32
Too-long frame receive TLFRCR
counter register
R/W H'FEF0 01F0* H'1EF0 01F0* 32
Residual-bit frame
RFCR
receive counter register
R/W H'FEF0 01F4* H'1EF0 01F4* 32
Multicast address frame MAFCR
receive counter register
R/W H'FEF0 01F8* H'1EF0 01F8* 32
IPG register
IPGR
R/W H'FEF0 0150* H'1EF0 0150* 32
Automatic PAUSE frame APR
register
R/W H'FEF0 0154* H'1EF0 0154* 32
Manual PAUSE frame MPR
register
R/W H'FEF0 0158* H'1EF0 0158* 32
Automatic PAUSE frame TPAUSER
retransmit count register
R/W H'FEF0 0164* H'1EF0 0164* 32
Random number
generation counter
upper limit setting
register
RDMLR
R/W H'FEF0 0140* H'1EF0 0140* 32
PAUSE Frame Receive RFCF
Counter Register
R/W H'FEF0 0160* H'1EF0 0160* 32
PAUSE frame retransmit TPAUSECR
counter register
R/W H'FEF0 0168* H'1EF0 0168* 32
Broadcast frame receive BCFRR
count setting register
R/W H'FEF0 016C* H'1EF0 016C* 32
Rev. 1.00 Nov. 22, 2007 Page 1524 of 1692
REJ09B0360-0100