SH7764 Datasheet, PDF (152/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
Table 5.2 States of Register in Each Operating Mode
Register Name
TRAPA exception register
Exception event register
Interrupt event register
Non-support detection exception register
Abbr.
TRA
EXPEVT
INTEVT
EXPMASK
Power-on Reset
Undefined
H'0000 0000
Undefined
H'0000 0000
Sleep
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
5.2.1 TRAPA Exception Register (TRA)
The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA
instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA
can also be modified by software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRACODE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R
R
Bit
Bit Name
31 to 10 
9 to 2 TRACODE
1, 0

Initial Value R/W
All 0
R
Undefined R/W
All 0
R
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
TRAPA Code
8-bit immediate data of TRAPA instruction is set
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
Rev. 1.00 Nov. 22, 2007 Page 96 of 1692
REJ09B0360-0100