SH7764 Datasheet, PDF (647/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
Table 17.4 ATAPI Interface Control Register Map
(These resisters are allocated to this module.)
Address
Register Name
Abbreviation
Access Register
Type Access Size*
H'FFF0 0080 ATAPI control
ATAPI_CONTROL
R/W 32
H'FFF0 0084 ATAPI status
ATAPI_STATUS
R/W 32
H'FFF0 0088 Interrupt enable
ATAPI_INT_ENABLE
R/W 32
H'FFF0 008C PIO timing
ATAPI_PIO_TIMING
R/W 32
H'FFF0 0090 Multiword DMA timing ATAPI_MULTI_TIMING
R/W 32
H'FFF0 0094 Ultra DMA timing
ATAPI_ULTRA_TIMING
R/W 32
H'FFF0 0098 Descriptor table base
address
ATAPI_DTB_ADR
R/W 32
H'FFF0 009C DMA start address
ATAPI_DMA_START_ADR R/W 32
H'FFF0 00A0 DMA transfer count
ATAPI_DMA_TRANS_CNT R/W 32
H'FFF0 00A4 ATAPI control 2
ATAPI_CONTROL2
R/W 32
H'FFF0 00A8 Reserved
R
32
H'FFF0 00AC Reserved
R
32
H'FFF0 00B0 ATAPI signal status
ATAPI_SIG_ST
R
32
H'FFF0 00BC Byte swap
ATAPI_BYTE_SWAP
R/W 32
Note: * These registers must be accessed in longwords (32 bits) by the CPU. Byte or word
accesses are prohibited.
[Legend]:
Initial value: Register value after reset
—:
Undefined value
R/W:
Readable and writable bit. The write value can be read.
R/WC0:
Readable and writable bit. When 0 is written, the bit is initialized. When 1 is written, it is
ignored.
R:
Read only register, only 0 should be written.
/W:
Write only bit. The read value is undefined.
All control/status registers are active high.
Rev. 1.00 Nov. 22, 2007 Page 591 of 1692
REJ09B0360-0100