SH7764 Datasheet, PDF (1309/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.12 Color Registers for Outside of Graphic Image Area (GROPBASERGB1 to
GROPBASERGB4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BASE_R[4:0]
BASE_G[5:0]
BASE_B[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 16 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 11 BASE_R 00000
R/W
These bits specify the R value for outside of the
[4:0]
graphic image area.
10 to 5 BASE_G 000000 R/W
[5:0]
These bits specify the G value for outside of the
graphic image area.
4 to 0 BASE_B 00000
R/W
These bits specify the B value for outside of the
[4:0]
graphic image area.
Note: This setting is valid only when VEN = 0 in GRCMEN.
Rev. 1.00 Nov. 22, 2007 Page 1253 of 1692
REJ09B0360-0100