SH7764 Datasheet, PDF (666/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.16 ATAPI Data Bus Alignment
Data bus alignment on the IO bus side
There is no difference between big and little endian settings.
Physical bus width: 3
Bus
Access
32-bit bus
31
16 8
0
31
Size
Byte
Address
4n
4n+1
4n+2
4n+3
Not specified
16-bit bus
16 8
0
Not specified
8-bit bus
31
16
8
0
Not specified
4n
Word _4n+2
Not specified
Not specified
Not specified
Longword
4n
B3 B2 B1 B0
Not specified
Not specified
B3: 31 to 24, B2: 23 to 16, B1: 15 to 8, and B0: 7 to 0
Data bus alignment on the pixel bus side
Bus width fixed at 32 bits; access size is longword
Data direction: ATAPI device Inside ATAPI Pixel-bus
ATAPI device
Cycle AT_DSD15-8
1 AT_DSD7-0
D1
D0
Cycle AT_DSD15-8 D3
2 AT_DSD7-0 D2
Inside ATAPI ^{31-24 23-16 15-08 07-00}
D1 D0 D3 D2
31-24 23-16 15-08 07-00
←
31-24 23-16 15-08 07-00
←
31-24 23-16 15-08 07-00
←
Pixel Bus ^{31-24 23-16 15-08 07-00}
D1 D0 D3 D2
WORDSWAPbit ←0
BYTESWAPbit: ←0
Not converted
31-24 23-16 15-08 07-00
D3 D2 D1 D0
Word swap
←1
←0
31-24 23-16 15-08 07-00
D0 D1 D2 D3
31-24 23-16 15-08 07-00
D2 D3 D0 D1
Byte swap
Word/byte swap
←0
←1
←1
←1
WORDSWAPbit ATAPIC control 2 Reg (bit1)
BYTESWAPbit: Byte Swap Reg (bit0)
Data direction: Pixel-Bus Inside ATAPI ATAPI device
Pixel Bus ^{31-24 23-16 15-08 07-00}
D1 D0 D3 D2
31-24 23-16 15-08 07-00
←
31-24 23-16 15-08 07-00
←
31-24 23-16 15-08 07-00
←
Inside ATAPI ^{31-24 23-16 15-08 07-00}
D1 D0 D3 D2
31-24 23-16 15-08 07-00
D3 D2 D1 D0
31-24 23-16 15-08 07-00
D0 D1 D2 D3
31-24 23-16 15-08 07-00
D2 D3 D0 D1
Cycle IDED15-8
D1
1 IDED7-0
D0
Cycle IDED15-8
D3
2 IDED7-0
D2
Not converted
WORDSWAPbit ←0
BYTESWAPbit: ←0
Cycle IDED15-8
D3
1 IDED7-0
D2
Cycle IDED15-8
D1
2 IDED7-0
D0
Word swap
←1
←0
Cycle IDED15-8
D0
1 IDED7-0
D1
Cycle IDED15-8
D2
1 IDED7-0
D3
Cycle IDED15-8
D2
2 IDED7-0
D3
Cycle IDED15-8
D0
2 IDED7-0
D1
Byte swap
Word/byte swap
←0
←1
←1
←1
WORDSWAPbit ATAPIC control 2 Reg (bit1)
BYTESWAPbit: Byte Swap Reg (bit0)
Figure 17.5 ATAPI Data Bus Alignment
Rev. 1.00 Nov. 22, 2007 Page 610 of 1692
REJ09B0360-0100