SH7764 Datasheet, PDF (1277/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Section 24 Video Display Controller (VDC2)
24.1 Overview
The video display controller (VDC2) provides functions for reading four planes of graphic images
(layers 1 to 4) stored in the external memory and overlaying them. It outputs 18-bit RGB video
(each color is represented by six bits) and digital video data conforming to BTA T-1004.
24.2 Features
Item
Operating frequency
Input image format
Display size
Display planes
α blending
Chroma-keying
Function
T-1004 display clock: 54 MHz
RGB666 display clock: 6.0 MHz to 36.0 MHz (depends on the display
panel size)
16-bit RGB565 progressive (SDRAM)
• 18-bit progressive RGB output
720 × 480 (NTSC)
720 × 576 (PAL)
320 × 240 (QVGA)
640 × 480 (VGA)
800 × 480 (WVGA)
• 8-bit digital output conforming to BTA T-1004 (parallel interface in the
8:4:4 bit format)
(the RGB data output timing can be set to the rising or falling edge of
the clock through the SYNCNT register setting)
720 × 480 (NTSC)
Up to four planes (layers 1 to 4)
Mixes layers 1 to 4 according to the transparency (α value).
Applies chroma-key processing to the specified RGB color (transparency
can be specified as the α value)
Rev. 1.00 Nov. 22, 2007 Page 1221 of 1692
REJ09B0360-0100