SH7764 Datasheet, PDF (1311/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.13 SG Mode Register (SGMODE)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WE 













Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
COM_ CDE_





 CDE_SEL _EXE

Initial value: 0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R
6
5
4
3
DE_ DEC_
 _{SEL MODE} 
0
0
0
0
R R/W R/W R
2
1
0
SYNC
 _{_SEL} 
0
0
0
R R/W R
Initial
Bit
Bit Name Value R/W
31
WE
0
R/W
30 to 10 
All 0
R
9
COM_CDE_ 0
R/W
SEL
8
CDE_EXE 0
R/W
7, 6

All 0
R
5
DE_SEL
0
R/W
Description
Enables register value transfer*¹. Writing 1 to this
bit transfers the register values (registers at
H'FFEB_0000 to H'FFEB_0208).
Reserved
These bits are always read as 0. The write value
should always be 0.
Selects the COM or CDE signal output.
0: Outputs COM
1: Outputs CDE
Enables CDE operation. This setting becomes
effective in synchronization with the internal Vsync
timing.
0: Disables CDE operation (0 is always output
through CDE when the COM_TYPE bit is 0 in
SYNCNT)
1: Enables CDE operation
Reserved
These bits are always read as 0. The write value
should always be 0.
Selects the DEH or DEC signal output.
0: Outputs DEH (horizontal data enable)
1: Outputs DEC (horizontal and vertical composite
data enable)
Rev. 1.00 Nov. 22, 2007 Page 1255 of 1692
REJ09B0360-0100