SH7764 Datasheet, PDF (354/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
14 to 12 WTS2 to 111 R/W
WTS0
11

0
R
10 to 8 WTH2 to 111 R/W
WTH0
7

0
R
Description
CSn Assert−WEn Assert Delay Cycle
These bits specify the number of cycles to be inserted
between the CSn assertion and the WEn assertion.
000: No cycles inserted (delay of 0.5 cycle)
001: 1 cycle inserted (delay of 1.5 cycles)
010: 2 cycles inserted (delay of 2.5 cycles)
011: 3 cycles inserted (delay of 3.5 cycles)
100: 4 cycles inserted (delay of 4.5 cycles)
101: 5 cycles inserted (delay of 5.5 cycles)
110: 6 cycles inserted (delay of 6.5 cycles)
111: 7 cycles inserted (delay of 7.5 cycles)
Reserved
This bit is always read as 0. The write value should
always be 0.
WEn Negate−CSn Negate Delay Cycle
These bits specify the number of cycles to be inserted
between the WEn negation and the CSn negation.
000: No cycles inserted (delay of 0.5 cycle)
001: 1 cycle inserted (delay of 1.5 cycles)
010: 2 cycles inserted (delay of 2.5 cycles)
011: 3 cycles inserted (delay of 3.5 cycles)
100: 4 cycles inserted (delay of 4.5 cycles)
101: 5 cycles inserted (delay of 5.5 cycles)
110: 6 cycles inserted (delay of 6.5 cycles)
111: 7 cycles inserted (delay of 7.5 cycles)
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 298 of 1692
REJ09B0360-0100