SH7764 Datasheet, PDF (1100/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.4.4 Setting the Display Resolution
The display resolution is set up in LDHCNR, LDHSYNR, LDVDLNR, LDVTLNR, and
LDVSYNR. The LCD current-alternating period for an STN or DSTN display is set by using the
LDACLNR. The initial values in these registers are typical settings for VGA (640 × 480 dots) on
an STN or DSTN display.
The clock to be used is set with the LDICKR. The LCD module frame rate is determined by the
display interval + retrace line interval (non-display interval) for one screen set in a size related
register and the frequency of the clock used.
This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the
beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last
line of the display). This function is set up by using the LDINTR.
22.4.5 Power-Supply Control Sequence
An LCD module normally requires a specific sequence for processing to do with the cutoff of the
input power supply. Settings in LDPMMR, LDPSPR, and LDCNTR, in conjunction with the LCD
power-supply control pins (LCD_VCPWC, LCD_VEPWC, and LCD_DON), are used to provide
processing of power-supply control sequences that suits the requirements of the LCD module.
Figures 22.4 to 22.7 are timing charts that show outlines of power-supply control sequences and
table 22.5 is a summary of available power-supply control sequence periods.
Rev. 1.00 Nov. 22, 2007 Page 1044 of 1692
REJ09B0360-0100