SH7764 Datasheet, PDF (420/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Table 12.3 State of Registers in Each Operating Mode
Channel Name
Abbreviation Power-on Reset
0
DMA source address SAR0
Undefined
register 0
DMA destination
address register 0
DAR0
Undefined
DMA transfer count
register 0
TCR0
Undefined
DMA channel control CHCR0
register 0
H'4000 0000
1
DMA source address SAR1
Undefined
register 1
DMA destination
address register 1
DAR1
Undefined
DMA transfer count
register 1
TCR1
Undefined
DMA channel control CHCR1
register 1
H'4000 0000
2
DMA source address SAR2
Undefined
register 2
DMA destination
address register 2
DAR2
Undefined
DMA transfer count
register 2
TCR2
Undefined
DMA channel control CHCR2
register 2
H'4000 0000
3
DMA source address SAR3
Undefined
register 3
DMA destination
address register 3
DAR3
Undefined
DMA transfer count
register 3
TCR3
Undefined
DMA channel control CHCR3
register 3
H'4000 0000
0 to 5
DMA operation
register
DMAOR
H'0000
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Module
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Nov. 22, 2007 Page 364 of 1692
REJ09B0360-0100