SH7764 Datasheet, PDF (74/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Classification
Bus control
Symbol
I/O
CS3 to CS0 O
BS
O
RD
O
R/W
O
RDY
I
WE0
O
WE1
O
WE2
O
WE2
O
Name
Function
Chip select 3 to 0 Chip-select signals for external
memory or devices.
Bus cycle start
Bus-cycle start signal. It is asserted
for the first of the multiple bus cycles
of a bus transaction.
Read
Indicates that data is read from an
external device.
Read/write
Indicates the read/write state for an
external device. It outputs a high
level for a read access or a low level
for a write access.
Wait
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
Byte select
Indicates a write access to bits 7 to 0
of data of an external memory or
device (for 8-, 16-, or 32-bit access).
This pin is multiplexed with
DQM64LL.
Byte select
Indicates a write access to bits 15 to
8 of data of an external memory or
device (for 16-, or 32-bit access).
This pin is multiplexed with
DQM64LU.
Byte select
Indicates a write access to bits 23 to
16 of data of an external memory or
device (for 16-, or 32-bit access).
This pin is multiplexed with
DQM64UL.
Byte select
Indicates a write access to bits 31 to
24 of data of an external memory or
device (for 8-, 16-, or 32-bit access).
This pin is multiplexed with
DQM64UU.
Rev. 1.00 Nov. 22, 2007 Page 18 of 1692
REJ09B0360-0100