SH7764 Datasheet, PDF (400/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
(c) Third-Step Arbitration
C: Arbitration is carried out between the SDRAM control such as refreshing and B. The
SDRAM control always takes priority.
(2) Access Order after Arbitration
In the three-step arbitration, care should be taken about the order of access execution since some
requests are selected from among multiple requests during the first- and second-step arbitration.
Specifically, there are access-request queues corresponding to A1 to A5 so that such arbitration is
carried out independently. The following gives a summary of queuing operations.
1. Memory control processing (C) is carried out.
2. The access (B) for which the priority has been determined and has been queued is executed.
3. One of A1 to A5 is selected (Ax) and queued as B.
4. The next arbitration is carried out between the modules corresponding to Ax selected in step 3
and the selected request (Ay) is queued.
However, it should be noted that Ay is not necessarily queued as B in the next arbitration here; it
depends on the result of the second-step arbitration (Az).
According to the above, the order of access execution is C, B, Ax, Az, … Az, and Ay.
When A5 is set to the priority level other than level 1, all the level-1 access requests are grouped
into A1. In addition, no requests with the other priority level are handled as A1 requests.
Therefore, when Ay has priority level 1 (i.e., A1) and Az has the other priority level, Ay takes
priority over Az and is selected, resulting in the execution order of C, B, Ax, and Ay (A1). Even if
level-1 access requests do not survive the first-step arbitration and are not selected as A1, the
execution order is C, B, Ax, A1, … A1, and Ay (A1).
Although other level-1 access requests take priority, it is all the same that level-1 access requests
are accepted after B and Ax for which the priority has been determined during the first- and
second-step arbitration.
For the symbols (A1 to A5, B, and C) for the multi-step arbitration circuit used in the above
descriptions, see figure 11.22 below.
Rev. 1.00 Nov. 22, 2007 Page 344 of 1692
REJ09B0360-0100