SH7764 Datasheet, PDF (214/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
7.2 Register Descriptions
The following registers are related to MMU processing.
Table 7.1 Register Configuration
Register Name
Abbreviation R/W P4 Address*
Area 7
Address*
Size
Page table entry high register
PTEH
R/W H'FF00 0000 H'1F00 0000 32
Page table entry low register
PTEL
R/W H'FF00 0004 H'1F00 0004 32
Translation table base register TTB
R/W H'FF00 0008 H'1F00 0008 32
TLB exception address register TEA
R/W H'FF00 000C H'1F00 000C 32
MMU control register
MMUCR
R/W H'FF00 0010 H'1F00 0010 32
Page table entry assistance
register
PTEA
R/W H'FF00 0034 H'1F00 0034 32
Physical address space control
register
PASCR
R/W H'FF00 0070 H'1F00 0070 32
Instruction re-fetch inhibit control IRMCR
register
R/W H'FF00 0078 H'1F00 0078 32
Note: * These P4 addresses are for the P4 area in the virtual address space. These area 7
addresses are accessed from area 7 in the physical address space by means of the
TLB.
Table 7.2 Register States in Each Processing State
Register Name
Page table entry high register
Page table entry low register
Translation table base register
TLB exception address register
MMU control register
Page table entry assistance
register
Physical address space control
register
Abbreviation
PTEH
PTEL
TTB
TEA
MMUCR
PTEA
PASCR
Power-on Reset Sleep
Undefined
Retained
Undefined
Retained
Undefined
Retained
Undefined
Retained
H'0000 0000
Retained
H'0000 xxx0
Retained
H'0000 0000
Retained
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Nov. 22, 2007 Page 158 of 1692
REJ09B0360-0100