SH7764 Datasheet, PDF (1058/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit
lines should be connected to GND or to the lowest bit from which data is output.
2. For details, see section 22.4.1, LCD Module Sizes which can be Displayed in this
LCDC.
Figure 22.1 shows a block diagram of LCDC.
LCD_CLK
Pck
Peripheral
bus
Clock
generator
DOTCLK
Register
LCDC
Pallet RAM
4 bytes × 256 entries
Bus interface
Power control
Line buffer
2.4 Kbytes
Normal output pin group
LCD_CL1
LCD_CL2
LCD_FLM
LCD_D15 to 0
LCD_DON
LCD_VCPWC
LCD_VEPWC
LCD_M_DISP
MCU
SDRAM controller
SDRAM
Figure 22.1 LCDC Block Diagram
Rev. 1.00 Nov. 22, 2007 Page 1002 of 1692
REJ09B0360-0100